chip_pin Verilog HDL Synthesis Attribute
A Verilog HDL synthesis attribute that assigns device pins to a port on a module.
To use the synthesis attribute in a , specify the synthesis attribute in between (* and *) delimiters in the same line as the Port Declaration for the input or output port to which you are assigning pins. The synthesis attribute value must be a string containing a list of device pin names separated by commas ().
You can use the synthesis attribute only on module ports with single-bit or one-dimensional types. For one-dimensional ports, the port's range declaration determines the mapping of pins listed in the synthesis attribute to individual bits in the port. For example, in the following code, the synthesis attribute assigns device pins to ports and on module :// Verilog-2001 attribute syntax
module foo(sel, data, o); (* chip_pin = "C4" *) input sel; (* chip_pin = "D1, D2, D3, D4" *) input [3:0] data; output o; // Specify module body endmodule
// Traditional comment-style syntax module foo(sel, data, o); input sel /* synthesis chip_pin = "C4" */; input [3:0] data; /* synthesis chip_pin = "D1, D2, D3, D4" */; output o; // Specify module body endmodule
In this example, is a one bit wide port; pin is assigned to this port. is a one-dimensional port that is four bits wide. Because is declared as , pin is assigned to , pin is assigned to , and so forth. If you declared as , pin would be assigned to , pin would assigned to , and so forth.
Note: The number of entries in the synthesis attribute's comma-delimited list must match the number of bits in the port. To leave a specific bit in a one-dimensional port unassigned, leave its corresponding pin assignment blank.
You cannot use the synthesis attribute to make pin assignments on instance ports, or module ports with more than two dimensions, such as memories.
This example implements a clocked bidirectional pin in Verilog HDL. The value of determines whether is an input, feeding in , or a tri-state, driving out the value .For more information on using this example in your project, go to:
bidir.vmodule bidirec (oe, clk, inp, outp, bidir); // Port Declaration input oe; input clk; input [7:0] inp; output [7:0] outp; inout [7:0] bidir; reg [7:0] a; reg [7:0] b; assign bidir = oe ? a : 8'bZ ; assign outp = b; // Always Construct always @ (posedge clk) begin b <= bidir; a <= inp; end endmodule
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